Design Verification

job description:

1. Design verification with SystemVerilog/UVM, C/C++
2. Integration test environment with VIP
3. Develop checker and scoreboard.
4. Verify design with SystemVerilog assertion.
5. Test plan for a verification task.

Requirement:

1. Familiar with SystemVerilog HDL, OOP, Python, TCL, and shell programming.
2. Better to have SoC design and bus concept.