Mission and History

Memory and storage are two distinct interfaces with complementary characteristics in computer architecture.  New technologies were created to bridge the performance/cost/capacity gap between memory and storage interfaces.  NAND was introduced some 30 years ago, and the SSDs improved the storage performance by several orders of magnitude beyond the earlier HDD’s.  Intel and Micron announced 3D XPoint in 2015 that claimed to have speed like DRAM and capacity and non-volatility like NAND.  Although commercially unsuccessful so far, the Storage-Class-Memory (SCM) like 3D Xpoint made strong impact and demonstration of its potential.

The architectural innovation in the memory and storage domain is not limited by new media/devices.  Compute Express Link (CXL), announced in 2019, is a new interface for Host-Accelerator coherency and Host-Memory interface, and CXL fabric further enables the disaggregated memory architecture.  To this day we are still in the early phase to appreciate the profound impact that CXL brings to the memory and storage space.  When Micron gave up on 3D XPoint in 2021, they announced that they will focus on CXL products instead.  But why would a new memory interface be compared to a new memory media?  With CXL, the Host no longer needs to manage the memory directly (like it does for a DDR memory) and the controller behind CXL will handle it.  As such, the Host is treating the CXL memory more like a storage device – in a way it is the vision of Storage-Class-Memory coming to fruition that the memory and storage are becoming similar to each other.

CXL is not only reshaping the server platforms by enabling memory sharing and pooling with far-memory, but it also has a huge potential of influencing the client/mobile/car segments.  Wolley is publishing a paper at FMS 2023 to promote “CXL native memory”, a memory chip that has CXL as the native interface.  We believe CXL native memory could be replacing LPDDR memory in the future, as it brings advantages in bandwidth, power consumption, IO footprint and application latency.  Coupled with UCIe, CXL native memory could also be very desirable for AI applications as it eliminates the CXL to DDR controller overhead.  Wolley also believes CXL could be a preferred interface for NVMe SSD, and we are preparing a paper on “NVMe over CXL (NVMe-oC)” that will be presented later in 2023.  Wolley is witnessing abundant opportunities with CXL, and we would love to collaborate with our partners to explore the architecture and implementation innovations.

Wolley started developing CXL controller in 2019, initially just for our SCM controller project.  With increasing market potential and external interest, we have invested continuously to build a complete CXL/PCIe controller IP.  Now the scope covers Gen1-6 PCIe line rate, x1/x2/x4/x8/x16 lanes, 256/512/1024-bit core, supporting RP/EP/USP/DSP configuration.  We also have an accompanying IDE IP in both PCIe and CXL mode.  Our controller IP passed PCI-SIG compliance and will pass CXL compliance test later in 2023.

Wolley just announced our newly formed CXL Design and Integration Services Group focusing on the ASIC and FPGA implementation.  Wolley is actively seeking partners to jointly develop and commercialize innovative products using CXL.  Wolley believes in a service model, and not an IP model, as the CXL IP now has a variety of configuration setting and application interfaces, and there could be many different ways of using the CXL IP in an architecture.  We are looking to serve our customers to achieve mutual success – we want to bring your core to the CXL world.