- SCM has better but still limited write endurance (105 – 108 depending on technology), and address mapping / wear leveling is required
- SCM needs to support SSD (block) mode and NVDIMM (memory) mode
- Traditional table-based address mapping / wear leveling is no good for NVDIMM (memory) mode – no matter the table is in host or device side Interface development, e.g., NVMe.
Wolley Value Proposition
- Innovative (patent approved 2018) SCM controller architectur
- New wear leveling scheme that does not require a mapping table
- Fundamental IP for NVDIMM using SCM
- SPOR (Sudden Power Loss Recovery) without super-cap
- Simplify hardware and FW design
- Reduce system size and cost
- Hardware based architecture offering superior performance
- PCIe memory mode prototype in FPGA (125MHz) shows 10-16M IOPs; we project
- ASIC performance to be over 30M IOPs for NVDIMM
- NVMe SSD prototype in FPGA (125MHz) shows over 800K IOPs; we project ASIC performance to be over 1M IOPs