Mission / History

Storage Class Memory (SCM) is a dream device for computer architecture as it has speed like DRAM and capacity and non-volatility like NAND.  Intel and Micron announced 3D XPoint in 2015 and Intel has since built SSD and NVDIMM products based on 3D XPoint.  Wolley was founded in 2016 with the conviction that SCM (such as 3D XPoint) is more suitable to use different controller architecture from the conventional table-based FTL used in NAND controllers. 

In the last two years, Wolley has developed a patented table-less SCM controller architecture employs fewer states than any of the existing controllers.  In addition to completely removing the need of the address table, it also removes the need of backup energy cap, and takes care of the difficult synchronization issue by design.  Implemented in FPGA (using DRAM to emulate SCM), this SCM controller demo platform has shown a promising performance comparable to Intel’s 3D X-point Optane.

In 2015, Intel and Micron announced the 3D Xpoint technology which bolstered SCM's feasibility and practicality. Storage Class Memory (SCM) holds great promise to be similar to DRAM in speed and interface, while analogous to NAND in density and non-volatility.   To realize its potential, SCM requires fundamentally different controller architecture than that of NAND for two important reasons.  First, a firmware-based NAND controller is more flexible and adaptive for wear leveling algorithms and device management, but too slow for SCM media.  Second, an address table based NAND controller requires ~0.1% of total storage capacity to map logical addresses into physical addresses in FTL.  Furthermore, the size of address table increases to ~6.4% of total memory capacity for in order to support 64-Byte access mode like accessing a DRAM in SCM applications, such as NVDIMM.

Wolley’s SCM Controller demo platform in FPGA has a PCIe-Gen3 x8 host interface @ 125MHz clock, with an emulated SCM capacity in 256GB, using two 128GB DIMMs, with inserted delay I FPGA to compensate for the SCM latency.  For validation purpose in FPGA, with 64-byte memory mode, the FPGA achieved 16.4M random read IOPs, and 10.2M random write IOPs.  With 4KB-byte block mode, it achieved 900K random read IOPs, and 800K random write IOPs.  It also demonstrated the ability to recovery from thousands of SPOR events, with a recovery time is in the order of 2-3 seconds.  With ASIC, the performance mentioned above can be significantly improved.

Wolley is actively seeking partners to jointly develop and commercialize the SCM controller in ASIC with SCM vendors.  Wolley has a solid track record of developing ECC and device management.  One of our current projects is implementing DDR frontend for NVDIMM products in datacenter SCM application.