- Storage Class Memory (SCM)
Storage Class Memory (SCM) is a revolutionary technology that brings together the benefits of traditional memory and storage devices. Some examples of SCM are like Phase Change Memory (PCM) and Resistive Random-Access Memory (ReRAM), both of which are the leading emerging memories for SCM.
Persistence (or non-volatility):
One of the key advantages of SCM is its ability to retain data even after a power loss, similar to storage. The persistence characteristic makes SCM particularly valuable for critical applications that demand data durability and non-volatility, such as in enterprise storage, databases, and transactional systems.
Similar to traditional memory, SCM allows data to be accessed and modified at the byte level. This fine-grained addressing capability makes SCM well-suited for memory-semantic applications.
- The Need for Wear-Leveling
Even if SCM brings remarkable advantages with its combination of speed, byte-addressability, and persistency, the physical cells in SCM can endure only a limited number of program (or read) cycles before its reliability starts to degrade. Eventually, if some memory cells experienced more cycles than others and lead to early wear-out, those failure cells may cause the SCM device unusable.
In order to extend the overall endurance of the SCM device, wear-leveling is one important technology to prevent specific cells from being excessively used and getting worn-out prematurely.
- Is wear-leveling different from techniques used by traditional SSD?
In SSDs, wear-leveling is usually implemented using tables to map logical addresses to physical ones, then manage to ensure an even wear across flash pages. However, the addressing unit of SCM is much smaller (often 64 bytes), which makes traditional table-based wear-leveling infeasible due to its impractical and huge table size.
- Wolley Table-less Wear-leveling
Table-less wear-leveling offers several advantages over traditional table-based approaches. In traditional SSD wear-leveling, large mapping tables necessitate costly, power-intensive memory, leading to complexity, while table-less wear-leveling can bypass those tables to reduce extra management effort.
First, our technology can eliminate the need for the management of mapping tables. Such an architecture also saves the implementation cost of storing the mapping table in SRAM.
Second, compared to the complex load/store scheme of a mapping table, usually done by firmware, the table-less address translation is directly performed in hardware.This reduces latency significantly and can deliver superior IOPS for both read and write.
Third, our table-less wear-leveling can excel in its effective implementation of Sudden-Power-Off-Recovery (SPOR). As the state transition is table-independent, the snapshot of the controller state that needs persistence could be very small. In short, our group-based and table-less management design streamlines the state transition process of the SCM controller and enhances the data reliability.